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1200 mhz to 2500 mhz, dual-balanced mixer, lo buffer, if amplifier, and rf balun ADL5356 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features rf frequency range of 1200 mhz to 2500 mhz if frequency range of 30 mhz to 450 mhz power conversion gain: 8.2 db ssb noise figure of 9.9 db ssb noise figure with 5 dbm blocker of 21 db input ip3 of 31 dbm input p1db of 11 dbm typical lo drive of 0 dbm single-ended, 50 rf and lo input ports high isolation spdt lo input switch single-supply operation: 3.3 v to 5 v exposed paddle, 6 mm 6 mm, 36-lead lfcsp applications cellular base station receivers transmit observation receivers radio link downconverters general description the ADL5356 uses a highly linear, doubly balanced, passive mixer core along with integrated rf and local oscillator (lo) balancing circuitry to allow single-ended operation. the ADL5356 incorporates the rf baluns, allowing for optimal performance over a 1200 mhz to 2500 mhz rf input frequency range. performance is optimized for rf frequencies from 1700 mhz to 2500 mhz using a low-side lo and rf frequencies from 1200 mhz to 1700 mhz using a high-side lo. the balanced passive mixer arrangement provides good lo-to-rf leakage, typically better than ?35 dbm, and excellent intermodulation performance. the balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. a high linearity if buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8.2 db and can be used with a wide range of output impedances. the ADL5356 provides two switched lo paths that can be used in tdd applications where it is desirable to ping-pong between two local oscillators. lo current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. for low voltage applications, the ADL5356 is capable of operation at voltages down to 3.3 v with substantially reduced current. under low voltage operation, an additional logic pin is provided to power down (<300 a) the circuit when desired. functional block diagram 2 3 1 36 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 4 6 7 5 8 9 26 25 27 24 22 21 23 20 19 ADL5356 07883-001 vgs0 vgs1 vgs2 losw pwdn vpos comm loi2 loi1 mnin mnct comm dvin vpos comm vpos comm dvct v p o s d v g m c o m m d v o p d v o n d v l e v p o s d v l g n c m n o n c o m m m n g m v p o s m n o p m n l e v p o s m n l g n c figure 1. the ADL5356 is fabricated using a bicmos high performance ic process. the device is available in a 6 mm 6 mm, 36-lead lfcsp and operates over a ?40c to +85c temperature range. an evaluation board is also available. table 1. passive mixers rf frequency (mhz) single mixer single mixer and if amp dual mixer and if amp 500 to 1700 adl5367 adl5357 adl5358 1200 to 2500 adl5365 adl5355 ADL5356
ADL5356 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 5 v performance ........................................................................... 4 ? 3.3 v performance ........................................................................ 4 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? 5 v performance ........................................................................... 7 ? 3.3 v performance ...................................................................... 15 ? spur tables .................................................................................. 16 ? circuit description......................................................................... 17 ? rf subsystem .............................................................................. 17 ? lo subsystem ............................................................................. 18 ? applications information .............................................................. 19 ? basic connections ...................................................................... 19 ? if port .......................................................................................... 19 ? bias resistor selection ............................................................... 19 ? mixer vgs control dac .......................................................... 19 ? evaluation board ............................................................................ 21 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 23 revision history 10/09revision 0: initial version
ADL5356 rev. 0 | page 3 of 24 specifications v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. table 2. parameter conditions min typ max unit rf input interface return loss tunable to >20 db over a limited bandwidth 15 db input impedance 50 rf frequency range 1200 2500 mhz output interface output impedance differential impedance, f = 200 mhz 230||0.75 ||pf if frequency range 30 450 mhz dc bias voltage 1 externally generated 3.3 5.0 5.5 v lo interface lo power ?6 0 +10 dbm return loss 13 db input impedance 50 lo frequency range 1230 2470 mhz power-down (pwdn) interface 2 pwdn threshold 1.0 v logic 0 level 0.4 v logic 1 level 1.4 v pwdn response time device enabled, if output to 90% of its final level 160 ns device disabled, supply current < 5 ma 230 ns pwdn input bias current device enabled 0 a device disabled 70 a 1 apply supply voltage from external circuit through choke inductors. 2 pwdn function is intended for use with v s 3.6 v only.
ADL5356 rev. 0 | page 4 of 24 5 v performance v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, vgs0 = vgs1 = vgs2 = 0 v, and z o = 50 , unless otherwise noted. table 3. parameter conditions min typ max unit dynamic performance power conversion gain including 4:1 if port transformer and pcb loss 7.5 8.2 8.5 db voltage conversion gain z source = 50 , differential z load = 200 differential 14.5 db ssb noise figure 9.9 db ssb noise figure under blocking 5 dbm blocker present 10 mhz from wanted rf input, lo source filtered 21 db input third-order intercept (iip3) f rf1 = 1899.5 mhz, f rf2 = 1900.5 mhz, f lo = 1697 mhz, each rf tone at ?10 dbm 25 31 dbm input second-order intercept (iip2) f rf1 = 1900 mhz, f rf2 = 1950 mhz, f lo = 1697 mhz, each rf tone at ?10 dbm 50 dbm input 1 db compression point (ip1db) 11 dbm lo-to-if leakage unfiltered if output ?24 dbm lo-to-rf leakage ?35 dbm rf-to-if isolation ?33 dbc if/2 spurious ?10 dbm input power ?75 dbc if/3 spurious ?10 dbm input power ?73 dbc if channel-to-channel isolation 50 db power supply positive supply voltage 4.75 5 5.25 v quiescent current lo supply 170 ma if supply 180 ma total quiescent current v s = 5 v 350 ma 3.3 v performance v s = 3.3 v, i s = 200 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.2 k, r2 = r5 = 400 , vgs0 = vgs1 = vgs2 = 0 v, and z o = 50 , unless otherwise noted. table 4. parameter conditions min typ max unit dynamic performance power conversion gain including 4:1 if port transformer and pcb loss 8.3 db voltage conversion gain z source = 50 , differential z load = 200 differential 14.6 db ssb noise figure 8.9 db input third-order intercept (iip3) f rf1 = 1899.5 mhz, f rf2 = 1900.5 mhz, f lo = 1697 mhz, each rf tone at ?10 dbm 21.2 dbm input second-order intercept (iip2) f rf1 = 1950 mhz, f rf2 = 1900 mhz, f lo = 1697 mhz, each rf tone at ?10 dbm 48 dbm input 1 db compression point (ip1db) 7 dbm power interface supply voltage 3.0 3.3 3.6 v quiescent current resistor programmable 200 ma total quiescent current device disabled 300 a
ADL5356 rev. 0 | page 5 of 24 absolute maximum ratings esd caution table 5. parameter rating supply voltage, v s 5.5 v rf input level 20 dbm lo input level 13 dbm mnop, mnon, dvop, dvon bias 6.0 v vgs2,vgs1,vgs0, losw, pwdn 5.5 v internal power dissipation 2.2 w ja 22c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering, 60 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADL5356 rev. 0 | page 6 of 24 pin configuration and fu nction descriptions 0 7883-002 24 25 26 23 22 21 1 2 3 9 20 27 19 4 5 6 7 8 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 3 3 3 4 3 5 3 6 3 2 3 1 3 0 2 9 2 8 vgs0 vgs1 vgs2 losw pwdn vpos comm loi2 loi1 mnin mnct comm dvin vpos comm vpos comm dvct v p o s d v g m c o m m d v o p d v o n d v l e v p o s d v l g n c m n o n c o m m m n g m v p o s m n o p m n l e v p o s m n l g n c ADL5356 top view (not to scale) notes 1 2 . nc = no connect. . exposed pad must be connected to ground. figure 2. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 mnin rf input for main channel. interna lly matched to 50 . must be ac-coupled. 2 mnct center tap for main channel input balun. bypass to ground using low inductance capacitor. 3, 5, 7, 12, 20, 34 comm device common (dc ground). 4, 6, 10, 16, 21, 30, 36 vpos positive supply voltage. 8 dvct center tap for diversity channel input balun. bypass to ground using low inductance capacitor. 9 dvin rf input for diversity channel. intern ally matched to 50 . must be ac-coupled. 11 dvgm diverstiy amplifier bias setting. connect 1.3 k resistor to ground for typical operation. 13, 14 dvop, dvon diversity channel differential open-collector o utputs. dvop and dvon should be pulled-up to vcc using external inductors. 15 dvle diversity channel if return. this pin must be grounded. 17 dvlg diverstiy channel lo buffer bias setting. conne ct 1 k resistor to ground for typical operation. 18, 28 nc no connect. 19 loi1 local oscillator input 1. internally matched to 50 . must be ac-coupled. 22 pwdn connect to ground for normal operation. connect pin to 3 v for disable mode when using vpos < 3.6 v. pwdn pin must be grounded when vpos > 3.6 v. 23 losw local oscillator input selection switch. set losw hi gh to select loi1 or set losw low to select loi2. 24, 25, 26 vgs0, vgs1, vgs2 gate to source control voltages. for typical operation, set vgs0, vgs1, and vgs2 to low logic level . 27 loi2 local oscillator input 2. internally matched to 50 . must be ac-coupled. 29 mnlg main channel lo buffer bias setting. connect 1 k resistor to ground for typical operation. 31 mnle main channel if return. this pin must be grounded. 32, 33 mnop, mnon main channel differential open-collector outputs. mnop and mnon should be pulled-up to vcc using external inductors. 35 mngm main amplifier bias setting. connect 1.3 k resistor to ground for typical operation. paddle epad exposed pad must be connected to ground.
ADL5356 rev. 0 | page 7 of 24 typical performance characteristics 5 v performance v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. supply current (ma) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 300 320 340 360 380 400 0 7883-003 t a = +85c t a = +25c t a = ?40c figure 3. supply current vs. rf frequency conversion gain (db) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 5 11 10 9 8 7 6 0 7883-004 t a = ?40c t a = +85c t a = +25c figure 4. power conversion gain vs. rf frequency input ip3 (dbm) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 15 20 25 30 35 40 45 0 7883-005 t a = +85c t a = +25c t a = ?40c figure 5 .input ip3 vs. rf frequency input ip2 (dbm) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 49 51 53 55 57 59 61 0 7883-006 t a = +85c t a = +25c t a = ?40c figure 6. input ip2 vs. rf frequency input p1db (dbm) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 0 7883-007 t a = +85c t a = +25c t a = ?40c figure 7. input p1db vs. rf frequency ssb noise figure (db) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 5 14 13 12 11 10 9 8 7 6 0 7883-008 t a = +85c t a = +25c t a = ?40c figure 8. ssb noise fi gure vs. rf frequency
ADL5356 rev. 0 | page 8 of 24 v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. supply current (ma) 300 400 380 360 340 320 ?40 ?20 ?10 ?30 0 10 20 30 40 50 60 70 80 temperature (c) 07883-009 v pos = 4.75v v pos = 5.00v v pos = 5.25v figure 9. supply current vs. temperature ?40 ?30 ?20 ?10 0 2010 30 40 50 60 70 80 conversion gain (db) temperature (c) 7.0 7.5 8.0 9.5 9.0 9.5 10.0 07883-010 4.75v 5.00v 5.25v figure 10. power conversion gain vs. temperature ?40 ?30 ?20 ?10 0 2010 30 40 50 60 70 80 input ip3 (dbm) 24 26 28 30 32 34 36 38 40 temperature (c) 07883-011 v pos = 5.25v v pos = 4.75v v pos = 5.0v figure 11. input ip3 vs. temperature ?40 ?30 ?20 ?10 0 2010 30 40 50 60 70 80 input ip2 (dbm) 49 50 52 53 54 55 56 57 58 51 temperature (c) 07883-012 v pos = 5.25v v pos = 4.75v v pos = 5.0v figure 12. input ip2 vs. temperature ?40 ?30 ?20 ?10 0 2010 30 40 50 60 70 80 input p1db (dbm) 8 9 10 11 12 14 13 temperature (c) v pos = 5.25v 07883-013 v pos = 4.75v v pos = 5.0v figure 13. input p1db vs. temperature 7.0 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 ssb noise figure (db) ?40 ?20 0 20 40 60 ?30 ?10 10 30 50 70 80 temperature (c) 07883-014 v pos = 4.75v v pos = 5.25v v pos = 5.0v figure 14. ssb noise figure vs. temperature
ADL5356 rev. 0 | page 9 of 24 v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. supply current (ma) if frequency (mhz) 30 80 130 180 230 280 330 430 380 400 300 320 340 360 380 0 7883-015 t a = +85c t a = +25c t a =?40c figure 15. supply current vs. if frequency conversion gain (db) 0 1 2 3 4 5 6 7 8 9 10 30 80 130 180 230 280 330 380 430 if frequency (mhz) 07883-016 t a = +85c t a = +25c t a = ?40c figure 16. power conversion gain vs. if frequency input ip3 (dbm) 0 5 10 15 20 25 30 35 40 30 80 130 180 230 280 330 380 430 if frequency (mhz) 07883-017 t a = +85c t a = +25c t a = ?40c figure 17. input ip3 vs. if frequency 40 70 65 60 55 50 45 30 80 130 180 230 280 330 380 430 input ip2 (dbm) if frequency (mhz) 07883-018 t a = +85c t a = +25c t a = ?40c figure 18. input ip2 vs. if frequency 8 13 12 11 10 9 14 30 80 130 180 230 280 330 380 430 input p1db (dbm) if frequency (mhz) 07883-019 t a = +85c t a = +25c t a = ?40c figure 19. input p1db vs. if frequency 6 14 13 12 11 10 9 8 7 30 80 130 180 230 280 330 380 430 ssb noise figure (db) if frequency (mhz) 07883-020 figure 20. ssb noise figure vs. if frequency
ADL5356 rev. 0 | page 10 of 24 v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. conversion gain (db) lo power (dbm) ?6 ?4 ?2 0 2 4 6 8 10 11 10 9 8 7 6 5 0 7883-021 t a = +25c t a = ?40c t a = +85c figure 21. power conversion gain vs. lo power input ip3 (dbm) lo power (dbm) ?6 ?4 ?2 0 2 4 6 8 10 40 38 36 34 32 30 28 26 24 22 20 0 7883-022 t a = +85c t a = +25c t a = ?40c figure 22. input ip3 vs. lo power input ip2 (dbm) 45 65 63 61 59 57 55 53 51 49 47 lo power ( dbm) ?6 ?4 ?2 0 2 4 6 8 10 07883-023 t a = +85c t a = +25c t a = ?40c figure 23. input ip2 vs. lo power input p1db (db) lo power (dbm) ?6 ?4 ?2 0 2 4 6 8 10 10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 0 7883-024 t a = +85c t a = +25c t a = ?40c figure 24. input p1db vs. lo power if/2 spurious (dbc) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2100 2200 ?85 ?80 ?75 ?70 ?65 ?60 ? 55 0 7883-025 t a = +85c t a = +25c t a = ?40c figure 25. if/2 spurious vs. rf frequency, rf power = ?10 dbm if/3 spurious (dbc) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2100 2200 ?75 ?74 ?73 ?72 ?71 ?70 ?69 ?68 ?67 ?66 ? 65 0 7883-026 t a = +85c t a = +25c t a = ?40c figure 26. if/3 spurious vs. rf frequency, rf power = ?10 dbm
ADL5356 rev. 0 | page 11 of 24 v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. 07883-027 100 7.6 7.8 8.0 8.2 8.4 8.6 8.8 80 60 40 20 0 percentage (%) conversion gain (db) mean = 8.26 sd = 0.31% figure 27. conversion gain distribution 07883-028 100 25 20 30 35 40 45 80 60 40 20 0 percentage (%) input ip3 lo (dbm) mean = 31.67 sd = 0.35% figure 28. input ip3 distribution 07883-029 100 10 11 12 13 80 60 40 20 0 percentage (%) input p1db (dbm) mean = 11.37 sd = 0.49% figure 29. input p1db distribution 07883-055 500 10 8 6 4 2 0 30 80 130 180 230 if frequency (mhz) 280 330 380 430 400 300 resistance ( ? ) capacitance (pf) 200 100 0 figure 30. if output impedanc e (r parallel c equivalent) 07883-031 30 25 20 15 10 5 0 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 rf port return loss (db) rf frequency (mhz) figure 31. rf port return loss, fixed if lo return loss (db) lo frequency (ghz) 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 25 0 5 10 15 20 selected unselected 0 7883-032 figure 32. lo return loss, selected and unselected
ADL5356 rev. 0 | page 12 of 24 v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. lo switch isolation (db) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 0 60 50 40 30 20 10 0 7883-033 t a = +85c t a = +25c t a =?40c figure 33. lo switch isolation vs. rf frequency rf-to-if isolation (db) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 40 38 36 34 32 30 28 26 0 7883-034 t a = +85c t a = +25c t a = ?40c figure 34. rf-to-if isolation vs. rf frequency lo-to-if leakage (dbm) ?40 ?35 ?30 ?25 ?20 ?15 ? 10 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 lo frequency (mhz) 07883-035 t a = +85c t a = +25c t a = ?40c figure 35. lo-to-if leakage vs. lo frequency lo-to-rf leakage (dbm) ?50 ?40 ?45 ?35 ?30 ?25 ?20 ? 15 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 lo frequency (mhz) 07883-036 t a = +85c t a = +25c t a = ?40c figure 36. lo-to-rf leakage vs. lo frequency 2xlo leakage (dbm) ?30 ? 16 ?18 ?20 ?22 ?24 ?26 ?28 lo frequency (mhz) 07883-037 2xlo-to-if 1500 1550 1600 1650 1700 1750 1800 1850 1900 1950 2000 2xlo-to-rf figure 37 . 2xlo leakage vs. lo frequency 07883-038 ?70 ? 35 ?40 ?45 ?50 ?55 ?60 ?65 3xlo leakage (dbm) lo frequency (mhz) 1500 1550 1650 1600 1750 1800 1700 2000 1950 1900 1850 3xlo-to-if 3xlo-to-rf figure 38. 3xlo leakage vs. lo frequency
ADL5356 rev. 0 | page 13 of 24 v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. 07883-039 4 10 6 18 16 14 12 10 8 9 8 7 6 5 conversion gain (db) ssb noise figure (db) rf frequency (mhz) vgs = 000 vgs = 011 vgs = 100 vgs = 110 1700 2200 2100 2000 1900 1800 1750 2150 2050 1950 1850 figure 39. power conversion gain and ssb noise figure vs. rf frequency for various vgs settings input p1db (db) input ip3 (db) rf frequency (mhz) 20 18 16 14 12 10 8 6 32 30 28 26 24 22 20 18 0 7883-040 vgs = 000 vgs = 011 vgs = 100 vgs = 110 1700 2200 2100 2000 1900 1800 1750 2150 2050 1950 1850 figure 40. input ip3 and input p1db vs . rf frequency for various vgs settings conversion gain and ssb noise figure (db) input ip3 (dbm) lo bias resistor value ( ? ) 600 1600 1500 1400 1300 1200 1100 1000900800700 13 12 11 10 9 8 7 6 35 30 25 20 15 10 5 0 conversion gain noise figure input ip3 0 7883-041 figure 41. power conversion gain, ssb noise figure, and input ip3 vs. lo bias resistor value ssb noise figure (db) blocker power (dbm) ?30 ?25 ?20 ?15 ?5 ?10 5 01 30 25 20 15 10 5 0 0 0 7883-042 figure 42. ssb noise figure vs. 10 mhz offset blocker level supply current (ma) bias resistor value ( ? ) 600 1600 1500 1400 1300 1200 1100 1000 900800700 0 50 100 150 200 250 300 350 lo resistor supply current if resistor supply current 0 7883-043 figure 43. lo and if supply current vs. if and lo bias resistor value conversion gain and ssb noise figure (db) input ip3 (dbm) if bias resistor value ( ? ) 600 1600 1500 1400 1300 1200 1100 1000900800700 13 12 11 10 9 8 7 6 35 30 25 20 15 10 5 0 conversion gain noise figure input ip3 0 7883-044 figure 44. power conversion gain, noise figure, and input ip3 vs. if bias resistor value
ADL5356 rev. 0 | page 14 of 24 v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.3 k, r2 = r5 = 1 k, z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. if channel-to-channel isolation (db) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 46 54 53 52 51 50 48 49 47 0 7883-051 t a = +85c t a = +25c t a =?40c figure 45. if channel-to-channel isolation vs. rf frequency
ADL5356 rev. 0 | page 15 of 24 3.3 v performance v s = 3.3 v, i s = 200 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, r1 = r4 = 1.2 k, r2 = r5 = 400 , z o = 50 , vgs0 = vgs1 = vgs2 = 0 v, unless otherwise noted. supply current (ma) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 190 195 200 205 210 215 0 7883-045 t a = +85c t a = +25c t a =?40c figure 46. supply current vs. rf frequency at 3.3 v conversion gain (db) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 4 11 10 9 8 7 6 5 0 7883-046 t a = +85c t a = +25c t a = ?40c figure 47. power conversion gain vs. rf frequency at 3.3 v input ip3 (dbm) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 10 30 28 26 24 22 20 18 16 14 12 0 7883-047 t a = +85c t a = +25c t a = ?40c figure 48. input ip3 vs. rf frequency at 3.3 v input ip2 (dbm) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 30 70 65 60 55 50 45 40 35 0 7883-048 t a = +85c t a = ?40c t a = +25c figure 49. input ip2 vs. rf frequency at 3.3 v input p1db (dbm) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 0 14 12 10 8 6 4 2 0 7883-049 t a = +85c t a = +25c t a = ?40c figure 50. input p1db vs. rf frequency at 3.3 v ssb noise figure (db) rf frequency (mhz) 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2 14 12 10 8 6 4 0 7883-050 t a = +85c t a = +25c t a = ?40c figure 51. ssb noise figure vs. rf frequency at 3.3 v
ADL5356 rev. 0 | page 16 of 24 spur tables all spur tables are (n f rf ) ? (m f lo ) and were measured using the standard evaluation board. mixer spurious products are measured in dbc from the if output power level. data was measured only fo r frequencies less than 6 ghz. typical noise floor of the measu rement system = ?100 dbm. 5 v performance v s = 5 v, i s = 350 ma, t a = 25c, f rf = 1900 mhz, f lo = 1697 mhz, lo power = 0 dbm, rf power = ?10 dbm, vgs0 = vgs1 = vgs2 = 0 v, and z o = 50 , unless otherwise noted. m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n 0 ?21.6 ?20.2 ?64.4 1 ?40.7 0.00 ?72.7 ?45.9 ?69.6 2 ?70.5 ?91.0 ?74.4 ?82.9 ?86.4 ADL5356 rev. 0 | page 17 of 24 circuit description the ADL5356 consists of two primary components: the radio frequency (rf) subsystem and the local oscillator (lo) subsystem. the combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. in addition, the need for external components is minimized, optimizing cost and size. the resulting balanced rf signal is applied to a passive mixer that commutates the rf input with the output of the lo subsystem. the passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. the only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (m n product) frequencies generated by the mixing process. terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the if amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. this termination is accomplished by the addition of a sum network between the if amplifier and the mixer and in the feedback elements in the if amplifier. the rf subsystem consists of integrated, low loss rf baluns, passive mosfet mixers, sum termination networks, and if amplifiers. the lo subsystem consists of an spdt-terminated fet switch and two multistage limiting lo amplifiers. the purpose of the lo subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the lo input. a block diagram of the device is shown in figure 52 . the if amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. the balanced open- collector output of the if amplifier, with impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or an analog-to-digital input while providing optimum second- order intermodulation suppression. the differential output impedance of the if amplifier is approximately 200 . if operation in a 50 system is desired, the output can be transformed to 50 by using a 4:1 transformer. 2 3 1 36 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 4 6 7 5 8 9 26 25 27 24 22 21 23 20 19 ADL5356 07883-001 vgs0 vgs1 vgs2 losw pwdn vpos comm loi2 loi1 mnin mnct comm dvin vpos comm vpos comm dvct v p o s d v g m c o m m d v o p d v o n d v l e v p o s d v l g n c m n o n c o m m m n g m v p o s m n o p m n l e v p o s m n l g n c the intermodulation performance of the design is generally limited by the if amplifier. the ip3 performance can be optimized by adjusting the if current with an external resistor. figure 41 , figure 43 , and figure 44 illustrate how various if and lo bias resistors affect the performance with a 5 v supply. additionally, dc current can be saved by increasing either or both resistors. it is permissible to reduce the dc supply voltage to as low as 3.3 v, further reducing the dissipated power of the part. (no performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.) figure 52. simplified schematic rf subsystem the single-ended, 50 rf input is internally transformed to a balanced signal using a low loss (<1 db) unbalanced-to-balanced (balun) transformer. this transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the rf port. although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. the rf balun can easily support an rf input frequency range of 1200 mhz to 2500 mhz.
ADL5356 rev. 0 | page 18 of 24 lo subsystem the lo amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation performance. the resulting amplifier provides extremely high performance centered on an operating frequency of 1700 mhz. the best operation is achieved with either low-side lo injection for rf signals in the 1700 mhz to 2500 mhz range or high-side injection for rf signals in the 1200 mhz to 1700 mhz range. operation outside these ranges is permissible, and conversion gain is extremely wideband, easily spanning 1200 mhz to 2500 mhz, but intermodulation is optimal over the aforementioned ranges. the ADL5356 has two lo inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. the two inputs are applied to a high isolation spdt switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the lo sources. this multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted lo input that may result in undesired if responses. the single-ended lo input is converted to a fixed amplitude differential signal using a multistage, limiting lo amplifier. this results in consistent performance over a range of lo input power. optimum performance is achieved from ?6 dbm to +10 dbm, but the circuit continues to function at considerably lower levels of lo input power. the performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. this is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. the bandwidth of the intermodulation performance is somewhat influenced by the current in the lo amplifier chain. for dc current sensitive applications, it is permissible to reduce the current in the lo amplifier by raising the value of the external bias control resistor. for dc current critical applications, the lo chain can operate with a supply voltage as low as 3.3 v, resulting in substantial dc power savings. in addition, when operating with supply voltages below 3.6 v, the ADL5356 has a power-down mode that permits the dc current to drop to <300 a. the logic inputs are designed to work with any logic family that provides a logic 0 input level of less than 0.4 v and a logic 1 input level that exceeds 1.4 v. all logic inputs are high impedance up to logic 1 levels of 3.3 v. at levels exceeding 3.3 v, protection circuitry permits operation up to 5.5 v, although a small bias current is drawn.
ADL5356 rev. 0 | page 19 of 24 applications information basic connections the ADL5356 mixer is designed to downconvert radio frequencies (rf) primarily between 1200 mhz and 2500 mhz to lower intermediate frequencies (if) between 30 mhz and 450 mhz. figure 53 depicts the basic connections of the mixer. it is recommended to ac-couple the rf and lo input ports to prevent non-zero dc voltages from damaging the rf balun or lo input circuit. the rfin matching network consists of a series 1.8 pf capacitor and a shunt 15 nh inductor to provide the optimized rf input return loss for the desired frequency band. if port the mixer differential if interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. the shunting impedance of the choke inductors used to couple dc current into the if amplifier should be selected to provide the desired output return loss. the real part of the output impedance is approximately 200 , as seen in figure 30 , which matches many commonly used saw filters without the need for a transformer. this results in a voltage conversion gain that is approximately 6 db higher than the power conversion gain, as shown in table 3 . when a 50 output impedance is needed, use a 4:1 impedance transformer, as shown in figure 53 . bias resistor selection the if bias resistors (r1 and r4) and lo bias resistors (r2 and r5) are used to adjust the bias current of the integrated amplifiers at the if and lo terminals. it is necessary to have a sufficient amount of current to bias both the internal if and lo amplifiers to optimize dc current vs. optimum iip3 performance. figure 41 , figure 43 , and figure 44 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and ip3 performance. mixer vgs control dac the ADL5356 features three logic control pins, vgs0 (pin 24), vgs1 (pin 25), and vgs2 (pin26), that allow programmability for internal gate-to-source voltages for optimizing mixer performance over desired frequency bands. the evaluation board defaults vgs0, vgs1, and vgs2 to ground. power conversion gain, nf, iip3, and input p1db can be optimized, as shown in figure 39 and figure 40 .
ADL5356 rev. 0 | page 20 of 24 2 3 1 36 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 4 6 7 5 8 9 26 25 27 24 22 21 23 20 19 ADL5356 vcc c3 c23 c2 r12 r13 r7 r16 vcc vcc vcc c22 c25 c18 c8 c21 r1 l1 l2 r3 l6 r2 main_in c9 z1 z2 div_in c11 z3 z4 c6 c7 lo2 c16 c34 r8 r14 r19 r15 r11 r17 vcc c26 c15 lo1 c14 vcc r4 r5 c24 c13 l3 vcc r9 c30 c31 t2 div_outp div_outn vcc c10 gnd + 07883-153 c1 c12 c28 r6 c20 l5 l4 c29 vcc r10 c33 c32 t1 main_outn main_outp c27 c19 c17 vcc figure 53. typical application circuit
ADL5356 rev. 0 | page 21 of 24 evaluation board an evaluation board is available for the family of double balanced mixers. the standard evaluation board schematic is shown in figure 54 . the evaluation board is fabricated using rogers? ro3003 material. table 7 describes the various configuration options of the evaluation board. evaluation board layout is shown in figure 55 and figure 56 . 07883-154 r1 l6 vcc c22 vcc c25 c18 r2 main_in c9 z1 z2 div_in c11 z3 z4 c3 c2 vcc c6 c7 lo2 c16 vcc r12 r13 r7 r16 c34 r8 r14 r19 r15 r11 r17 vcc c26 c15 lo1 c14 c23 vcc r4 r5 l3 c24 c13 vcc vcc c10 gnd + r9 c30 c31 t2 div_outp div_outn c1 c12 c28 r6 c20 l5 l4 c29 vcc c8 c21 l1 l2 r3 r10 c33 c32 t1 main_outn main_outp c27 c19 c17 vcc vgs0 vgs1 vgs2 losw pwdn vpos comm loi2 loi1 mnin mnct comm dvin vpos comm vpos comm dvct v p o s d v g m c o m m d v o p d v o n d v l e v p o s d v l g n c m n o n c o m m m n g m v p o s m n o p m n l e v p o s m n l g n c ADL5356 top view (not to scale) figure 54. evaluation board schematic
ADL5356 rev. 0 | page 22 of 24 table 7. evaluation board configuration components description default conditions c1, c8, c10, c12, c13, c15, c18, c21, c22, c23, c24, c25, c26 power supply decoupling. nominal supply decoupling consists of a 0.01 f capacitor to ground in parallel with 10 pf capacitors to ground positioned as close to the device as possible. c10 = 4.7 f (size 3216), c1, c8, c12, c21 = 150 pf (size 0402), c22, c23, c24, c25, c26 = 10 pf (size 0402), c13, c15, c18 = 0.1 f (size 0402) z1 to z4, c2, c3, c6, c7, c9, c11 rf main and diversity input interface. main and diversity input channels are ac-coupled through c9 and c11. z1 to z4 provide additional component placement for external matching/filter networks. c2, c3, c6, and c7 provide bypassing for the center taps of the main and diversity on-chip input baluns. c2, c7 = 10 pf (size 0402), c3, c6 = 0.01 f (size 0402), c9, c11 = 1.8 pf (size 0402), z2, z4 = 15 nh, z1, z3 = open (size 0402) t1, t2, c17, c19, c20, c27 - c33, l1, l2, l4, l5, r3, r6, r9, r10 if main and diversity output interface. the open collector if output interfaces are biased through pull-up choke inductors l1, l2, l4, and l5, with r3 and r6 available for additional supply bypassing. t1 and t2 are 4:1 impedance transformers used to provide a single-ended if output interface with c27 and c28 providing center-tap bypassing. c17, c19, c20, c29, c30, c31, c32, and c33 ensure an ac-coupled output interface. remove r9 and r10 for balanced output operation. c17, c19, c20, c29 to c33 = 0.001 f (size 0402), c27, c28 = 150 pf (size 0402), t1, t2 = tc4-1t+ (mini-circuits), l1, l2, l4, l5 = 330 nh (size 0805), r3, r6, r9, r10 = 0 (size 0402) c14, c16, r15, losel lo interface. c14 and c16 provide ac coupling for the loi1 and loi2 local oscillator inputs. losel selects the appropriate lo input for both mixer cores. r15 provides a pull-down to ensure loi2 is enabled when the losel jumper is removed. jumper can be removed to allow losel interface to be exercised using external logic generator. c14, c16 = 10 pf (size 0402), r15 = 10 k (size 0402), losel = 2-pin shunt r19, pwdn pwdn interface. when the pwdn 2-pin shunt is inserted, the ADL5356 is powered down. when r19 is open, it pulls the pwdn logic low and enables the device. jumper can be removed to allow pwdn interface to be excercised using an external logic generator. grounding the pwdn pin is allowed during nominal operation but is not permitted when supply voltages exceed 3.3 v. r19 = 10 k (size 0402), pwdn = 2-pin shunt r1, r2, r4, r5, l3, l6, r7, r8, r11 to r14, r16, r17, c34 bias control. r16 and r17 form a voltage divider to provide a 3 v for logic control, bypassed to ground through c34. r7, r8, r11, r12, r13, and r14 provide resistor programmability of vgs0, vgs1, and vgs2. typically, these nodes can be hardwired for nominal operation. grounding these pins is allowed for nominal operation. r2 and r5 set the bias point for the internal lo buffers. r1 and r4 set the bias point for the internal if amplifiers. l3 and l6 are external inductors used to improve isolation and common-mode rejection. r1, r4 = 1.3 k (size 0402), r2, r5 = 1 k (size 0402), l3, l6 = 0 (size 0603), r12, r13, r14 = open (size 0402), r7, r8, r11 = 0 (size 0402), r16 = 10 k (size 0402), r17 = 15 k (size 0402), c34 = 1 nf (size 0402) 0 7883-056 figure 55. evaluation board top layer 0 7883-057 figure 56. evaluation board bottom layer
ADL5356 rev. 0 | page 23 of 24 outline dimensions compliant to jedec standards mo-220-vjjd-1 050808-d 1 36 9 10 28 27 19 18 3.85 3.70 sq 3.55 top view 6.00 bsc sq 5.75 bsc sq coplanarity 0.08 4.00 ref 0.75 0.60 0.50 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.20 min exposed pad (bottom view) pin 1 indicator 0.35 0.28 0.23 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 57. 36-lead lead frame chip scale package [lfcsp_vq] 6mm 6 mm body, very thin quad (cp-36-1) dimensions shown in millimeters ordering guide model temperature range packag e description package option ADL5356acpz-r2 1 ?40c to +85c 36-lead lfcsp_vq cp-36-1 ADL5356acpz-r7 1 ?40c to +85c 36-lead lfcsp_vq cp-36-1 ADL5356-evalz 1 evaluation board 1 z = rohs compliant part.
ADL5356 rev. 0 | page 24 of 24 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07883-0-10/09(0)

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